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Hardware-based Byte-code Interpreters: Are they all they are cracked up to be?

Today I was made aware that Intel is amidst an initiative to create chips capable of interpreting Java byte-code in the same way a normal ship would interpret assembly.  Now I really don't know much about chips but upon hearing this I thought to myself "Wow... that's really going to make Java's performance skyrocket past .NET's."  I mentioned this to one of my trainer instructors (I'm still in training at work) who in turn told me he didn't believe this was such a big deal or a big gain for Java.  I was shocked to hear that but I listened to his justification which makes sense but again I don't know much about chips.  His basic concept was two-fold: 1) What's the performance gain over having the byte-code compiled to native code at install time?  2) Any performance gain that the JITter might introduce with runtime optimization would be missed.  Another training instructor put his two cents in as well but he was more on the side that having hardware capable of bypassing the JITter would improve performance.

I was under the impression that having hardware with these capabilities would unquestionably make Java's speed a force to be reckoned with.  I do however see the point that it really doesn't seem to buy you much over having byte-code compiled down to native code at install time. 

Does anyone know if there are any initiatives of this kind for IL?  Does the skeptical instructor have a valid point?  General feedback anyone?

Posted: Mar 10 2004, 11:30 PM by SamerEyeWarrior | with 5 comment(s)
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Comments

Raymond Chen said:

It's an interesting idea, but remember that a lot of optimization is not available until JIT time. For example, if you call a method that happens to be small and final, it can be inlined by the JITter. The compiler can't inline the function because you might decide to recompile that method later and change that small final function.

Also, the virtual machine uses a stack engine, so "c=a+b" would be "push a; push b; add; pop c". That's nine memory accesses (load a, push a; load b, push b; pop arg1, pop arg2, add, push result; pop result, store c). a JITter would reduce that to just three (load a, load b, add, store c).

It's an interesting idea, but it's not a slam dunk.

(This isn't the first time somebody tried to make a processor that executed p-code natively. http://www.moorecad.com/standardpascal/p4.html )
# March 11, 2004 12:44 AM

Jonathan Hardwick said:

The idea has been around for a while. Sun made a lot of noise about it back in 1996/97 - just google for "sun java chip". For an earlier analysis, see this Byte article: http://www.byte.com/art/9611/sec6/art2.htm. It didn't live up to the initial hype, but Sun still license the "picojava" technology: http://www.sun.com/microelectronics/picoJava/.
# March 11, 2004 2:29 AM

Brad Wilson said:

The skeptical instructor is right to be skeptical. You trade the JIT time (minimal) against the lack of optimizations at JIT time; that's a terrible trade off.

I can't possibly imagine how this could pay off. Even the smallest devices like cell phones are probably better off with a general purpose CPU. Certainly, for general computational devices like a PC, this would never EVER fly.
# March 11, 2004 4:12 AM

Lorenzo Barbieri said:

I think that one point that slows the execution of IL code is the CAS and all the related security checks.
I don't know if these checks can be optimized using hardware execution instead of JITing.
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